Cascaded PLL design for a 90nm CMOS high performance microprocessor

PLL clock generators are designed for a third-generation NetBurst/spl trade/ processor implemented in a 90nm CMOS process. A cascade configuration offers improved jitter attenuation and facilitates a wide synthesis range. Parameter design takes into account a dual-sloped VCO control. A new charge pu...

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Bibliographic Details
Main Authors: Wong, K.L., Fayneh, E., Knoll, E., Law, R.H., Lim, C.H., Parker, R.J., Feng Wang, Cangsang Zhao
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Clocks
Damping
Filters
Frequency
Jitter
Microprocessors
Phase locked loops
Voltage control
Voltage-controlled oscillators
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Description
Summary:PLL clock generators are designed for a third-generation NetBurst/spl trade/ processor implemented in a 90nm CMOS process. A cascade configuration offers improved jitter attenuation and facilitates a wide synthesis range. Parameter design takes into account a dual-sloped VCO control. A new charge pump topology offers superior symmetry.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2003.1234366