Platform-based testbench generation

This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting gen...

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Bibliographic Details
Main Authors: Henftling, R., Zinn, A., Bauer, M., Ecker, W., Zambaldi, M.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Control system synthesis
Design automation
Field programmable gate arrays
Hardware
Logic design
Protocols
Test pattern generators
Testing
Topology
Online Access:Request full text
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Description
Summary:This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2003.1253741