A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2004-01, Vol.39 (1), p.194-206
Main Authors: Hamamoto, T., Furutani, K., Kubo, T., Kawasaki, S., Iga, H., Kono, T., Konishi, Y., Yoshihara, T.
Format: Article
Language:English
Subjects:
Architecture
Boundaries
Circuit testing
Circuits
Clocks
Delay
Delay lines
Digital
DRAM chips
Dynamic link libraries
Frequency
High-speed electronics
Jitter
Random access memory
SDRAM
Timing
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Summary:This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-/spl mu/m DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2003.820851