The design of a high speed ASIC unit for the hash function SHA-256 (384, 512)

After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the p...

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Bibliographic Details
Main Authors: Dadda, L., Macchetti, M., Owen, J.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Algorithm design and analysis
Application specific integrated circuits
Circuit synthesis
Delay
Hardware
Microelectronics
NIST
Partitioning algorithms
Pipeline processing
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Description
Summary:After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2004.1269207