How far will silicon nanocrystals push the scaling limits of NVMs technologies?

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretic...

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Main Authors: De Salvo, B., Gerardi, C., Lombardo, S., Baron, T., Perniola, L., Mariolle, D., Mur, P., Toffoli, A., Gely, M., Semeria, M.N., Deleonibus, S., Ammendola, G., Ancarani, V., Melanotte, M., Bez, R., Baldi, L., Corso, D., Crupi, I., Puglisi, R.A., Nicotra, G., Rimini, E., Mazen, F., Ghibaudo, G., Pananakakis, G., Compagnoni, C.M., Ielmini, D., Lacaita, A., Spinelli, A., Wan, Y.M., van der Jeugd, K.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
CMOS technology
Electrons
Fluctuations
Nanocrystals
Nonvolatile memory
Research and development
Silicon
Surface treatment
Testing
Threshold voltage
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Summary:For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
DOI:10.1109/IEDM.2003.1269352