1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications

A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achiev...

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Bibliographic Details
Main Authors: Yu-Cherng Hung, Chung-Yang Tsai, Bin-Da Liu
Format: Conference Proceeding
Language:English
Subjects:
Circuit simulation
CMOS analog integrated circuits
CMOS technology
Delay
Dynamic range
Input variables
Rail to rail inputs
Signal resolution
Very large scale integration
Voltage
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Summary:A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-/spl mu/m CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 /spl mu/s under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.
DOI:10.1109/ICNNSP.2003.1279278