A multi-gigabit CMOS serial link transceiver using jitter tolerant Delay Locked Loop

A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase d...

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Main Authors: Byeong-Chun So, Won-Suk Hwang, Soo-Won Kim
Format: Conference Proceeding
Language:English
Subjects:
Charge pumps
Circuits
Clocks
Delay
Detectors
Jitter
Phase detection
Phase locked loops
Sampling methods
Transceivers
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Won-Suk Hwang
Soo-Won Kim
description A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25 /spl mu/m CMOS technology. It is capable of recovering data at a speed of 2.5 Gbps.
doi_str_mv 10.1109/EDSSC.2003.1283508
format conference_proceeding
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ispartof 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668), 2003, p.171-174
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Charge pumps
Circuits
Clocks
Delay
Detectors
Jitter
Phase detection
Phase locked loops
Sampling methods
Transceivers
title A multi-gigabit CMOS serial link transceiver using jitter tolerant Delay Locked Loop
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