Loading…

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-ar...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2004-04, Vol.52 (4), p.1244-1251
Main Authors: Carchon, G.J., Walter De Raedt, Beyne, E.
Format: Article
Language:English
Subjects:
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c350t-a83c94079d8594b5fc04bc4d0450b39bc6a31b6e2f0f1000bcd3ec8e6f6158b3
cites cdi_FETCH-LOGICAL-c350t-a83c94079d8594b5fc04bc4d0450b39bc6a31b6e2f0f1000bcd3ec8e6f6158b3
container_end_page 1251
container_issue 4
container_start_page 1244
container_title IEEE transactions on microwave theory and techniques
container_volume 52
creator Carchon, G.J.
Walter De Raedt
Beyne, E.
description In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.
doi_str_mv 10.1109/TMTT.2004.825656
format article
fullrecord <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_ieee_primary_1284795</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1284795</ieee_id><sourcerecordid>28675623</sourcerecordid><originalsourceid>FETCH-LOGICAL-c350t-a83c94079d8594b5fc04bc4d0450b39bc6a31b6e2f0f1000bcd3ec8e6f6158b3</originalsourceid><addsrcrecordid>eNqNkU1LxDAQhoMouK7eBS_Bg7eukzZJ06MsfsGKCAWPIU3TNms3WZOusP_elhUET56Gged9meFB6JLAghAobsuXslykAHQhUsYZP0IzwlieFDyHYzQDICIpqIBTdBbjelwpAzFD5btqTEh682V6vFX6Q7XWtXgwunO-9-0eNz7gzrZd8oa9S3Rnt9i6eqcHHyJWrsZDUC5ubIzWO9xbZ-I5OmlUH83Fz5yj8uG-XD4lq9fH5-XdKtEZgyFRItMFhbyoBStoxRoNtNK0hvG0KisqzVVGKm7SBhoCAJWuM6OF4Q0nTFTZHN0carfBf-5MHOR4hTZ9r5zxuyhTIThPOfsHyHPG02wEr_-Aa78LbvxBCkEJcFZMbXCAdPAxBtPIbbAbFfaSgJxcyMmFnFzIg4sxcnWIWGPML54Kmo-F35-BhXc</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>884106595</pqid></control><display><type>article</type><title>Wafer-level packaging technology for high-Q on-chip inductors and transmission lines</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Carchon, G.J. ; Walter De Raedt ; Beyne, E.</creator><creatorcontrib>Carchon, G.J. ; Walter De Raedt ; Beyne, E.</creatorcontrib><description>In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.</description><identifier>ISSN: 0018-9480</identifier><identifier>EISSN: 1557-9670</identifier><identifier>DOI: 10.1109/TMTT.2004.825656</identifier><identifier>CODEN: IETMAB</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Dielectric substrates ; Inductors ; Loss measurement ; Packaging ; Passivation ; Resonance ; Resonant frequency ; Semiconductors ; Silicon ; Transmission line measurements ; Transmission lines ; Wafer scale integration</subject><ispartof>IEEE transactions on microwave theory and techniques, 2004-04, Vol.52 (4), p.1244-1251</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c350t-a83c94079d8594b5fc04bc4d0450b39bc6a31b6e2f0f1000bcd3ec8e6f6158b3</citedby><cites>FETCH-LOGICAL-c350t-a83c94079d8594b5fc04bc4d0450b39bc6a31b6e2f0f1000bcd3ec8e6f6158b3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1284795$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,27901,27902,54771</link.rule.ids></links><search><creatorcontrib>Carchon, G.J.</creatorcontrib><creatorcontrib>Walter De Raedt</creatorcontrib><creatorcontrib>Beyne, E.</creatorcontrib><title>Wafer-level packaging technology for high-Q on-chip inductors and transmission lines</title><title>IEEE transactions on microwave theory and techniques</title><addtitle>TMTT</addtitle><description>In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.</description><subject>Dielectric substrates</subject><subject>Inductors</subject><subject>Loss measurement</subject><subject>Packaging</subject><subject>Passivation</subject><subject>Resonance</subject><subject>Resonant frequency</subject><subject>Semiconductors</subject><subject>Silicon</subject><subject>Transmission line measurements</subject><subject>Transmission lines</subject><subject>Wafer scale integration</subject><issn>0018-9480</issn><issn>1557-9670</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><recordid>eNqNkU1LxDAQhoMouK7eBS_Bg7eukzZJ06MsfsGKCAWPIU3TNms3WZOusP_elhUET56Gged9meFB6JLAghAobsuXslykAHQhUsYZP0IzwlieFDyHYzQDICIpqIBTdBbjelwpAzFD5btqTEh682V6vFX6Q7XWtXgwunO-9-0eNz7gzrZd8oa9S3Rnt9i6eqcHHyJWrsZDUC5ubIzWO9xbZ-I5OmlUH83Fz5yj8uG-XD4lq9fH5-XdKtEZgyFRItMFhbyoBStoxRoNtNK0hvG0KisqzVVGKm7SBhoCAJWuM6OF4Q0nTFTZHN0carfBf-5MHOR4hTZ9r5zxuyhTIThPOfsHyHPG02wEr_-Aa78LbvxBCkEJcFZMbXCAdPAxBtPIbbAbFfaSgJxcyMmFnFzIg4sxcnWIWGPML54Kmo-F35-BhXc</recordid><startdate>200404</startdate><enddate>200404</enddate><creator>Carchon, G.J.</creator><creator>Walter De Raedt</creator><creator>Beyne, E.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>8BQ</scope><scope>JG9</scope></search><sort><creationdate>200404</creationdate><title>Wafer-level packaging technology for high-Q on-chip inductors and transmission lines</title><author>Carchon, G.J. ; Walter De Raedt ; Beyne, E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c350t-a83c94079d8594b5fc04bc4d0450b39bc6a31b6e2f0f1000bcd3ec8e6f6158b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Dielectric substrates</topic><topic>Inductors</topic><topic>Loss measurement</topic><topic>Packaging</topic><topic>Passivation</topic><topic>Resonance</topic><topic>Resonant frequency</topic><topic>Semiconductors</topic><topic>Silicon</topic><topic>Transmission line measurements</topic><topic>Transmission lines</topic><topic>Wafer scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Carchon, G.J.</creatorcontrib><creatorcontrib>Walter De Raedt</creatorcontrib><creatorcontrib>Beyne, E.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>METADEX</collection><collection>Materials Research Database</collection><jtitle>IEEE transactions on microwave theory and techniques</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Carchon, G.J.</au><au>Walter De Raedt</au><au>Beyne, E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Wafer-level packaging technology for high-Q on-chip inductors and transmission lines</atitle><jtitle>IEEE transactions on microwave theory and techniques</jtitle><stitle>TMTT</stitle><date>2004-04</date><risdate>2004</risdate><volume>52</volume><issue>4</issue><spage>1244</spage><epage>1251</epage><pages>1244-1251</pages><issn>0018-9480</issn><eissn>1557-9670</eissn><coden>IETMAB</coden><abstract>In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TMTT.2004.825656</doi><tpages>8</tpages></addata></record>
fulltext fulltext
identifier ISSN: 0018-9480
ispartof IEEE transactions on microwave theory and techniques, 2004-04, Vol.52 (4), p.1244-1251
issn 0018-9480
1557-9670
language eng
recordid cdi_ieee_primary_1284795
source IEEE Electronic Library (IEL) Journals
subjects Dielectric substrates
Inductors
Loss measurement
Packaging
Passivation
Resonance
Resonant frequency
Semiconductors
Silicon
Transmission line measurements
Transmission lines
Wafer scale integration
title Wafer-level packaging technology for high-Q on-chip inductors and transmission lines
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T23%3A56%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Wafer-level%20packaging%20technology%20for%20high-Q%20on-chip%20inductors%20and%20transmission%20lines&rft.jtitle=IEEE%20transactions%20on%20microwave%20theory%20and%20techniques&rft.au=Carchon,%20G.J.&rft.date=2004-04&rft.volume=52&rft.issue=4&rft.spage=1244&rft.epage=1251&rft.pages=1244-1251&rft.issn=0018-9480&rft.eissn=1557-9670&rft.coden=IETMAB&rft_id=info:doi/10.1109/TMTT.2004.825656&rft_dat=%3Cproquest_ieee_%3E28675623%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c350t-a83c94079d8594b5fc04bc4d0450b39bc6a31b6e2f0f1000bcd3ec8e6f6158b3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=884106595&rft_id=info:pmid/&rft_ieee_id=1284795&rfr_iscdi=true