VHDL-AMS modeling of a new PLL with an inverse sine phase detector (ISPD PLL)

For improving the performance of PLL, a sin/sup -1/(x) function generator has been substituted for a standard phase detector. The behavior of blocks have been modeled with VHDL-AMS at different abstraction levels and compared with experimental results. We point out that connections between the block...

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Bibliographic Details
Main Authors: Karray, M., Seon, J.K., Charlot, J.-J., Nasmoudi, N.
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Detectors
Equations
Frequency
Mathematical model
Phase detection
Phase locked loops
Signal generators
Steady-state
Voltage-controlled oscillators
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Summary:For improving the performance of PLL, a sin/sup -1/(x) function generator has been substituted for a standard phase detector. The behavior of blocks have been modeled with VHDL-AMS at different abstraction levels and compared with experimental results. We point out that connections between the blocks may need some (impedance) adaptation and physical accurate models may not be absolutely necessary for an accurate simulation of the loop.
DOI:10.1109/BMAS.2002.1291062