Reliable low-power digital signal processing via reduced precision redundancy

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2004-05, Vol.12 (5), p.497-510
• Main Authors: Byonghyo Shim, Sridhara, S.R., Shanbhag, N.R.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Design. Technologies. Operation analysis. Testing; Digital filters; Digital signal processing; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy conservation; Exact sciences and technology; Fast Fourier transforms; Filtering; Frequency filters; Impulse response; Integrated circuits; Integrated circuits by function (including memories and processors); Noise reduction; Quadrature phase shift keying; Redundancy; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal processing algorithms; Signal to noise ratio; Testing, measurement, noise and reliability; Very large scale integration; Voltage
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2004.826201

In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% energy savings with no loss in the signal-to-noise ratio (SNR) for receive filtering in a QPSK system and the butterfly of fast Fourier transform (FFT) in a WLAN OFDM system, respectively. These energy savings are with respect to optimally scaled (i.e., the supply voltage equals the critical voltage V/sub dd-crit/) present day systems. Further, we show that the RPR technique is able to maintain the output SNR for error rates of up to 0.09/sample and 0.06/sample in an finite impulse response filter and a FFT block, respectively.