Partitioning algorithms for layout synthesis from register-transfer netlists

A sliced-layout architecture is presented to alleviate the problems of the general bit-sliced layouts. Also described are partitioning algorithms that are used to generate the floorplan for this layout architecture. The partitioning algorithms not only select the best suited layout style for each co...

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Bibliographic Details
Main Authors: Wu, A.C.H., Gajski, D.D.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Counting circuits
Flip-flops
Integrated circuit synthesis
Latches
Multiplexing
Partitioning algorithms
Registers
Routing
Switches
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Description
Summary:A sliced-layout architecture is presented to alleviate the problems of the general bit-sliced layouts. Also described are partitioning algorithms that are used to generate the floorplan for this layout architecture. The partitioning algorithms not only select the best suited layout style for each component, but also consider critical paths, I/O pin locations, and connections between logic blocks. This approach improves the overall area utilization and minimizes the total wire length.< >
DOI:10.1109/ICCAD.1990.129864