Understanding yield losses in logic circuits

Yield improvement requires understanding failures and identifying potential sources of yield loss. We focus on diagnosing random logic circuits and classifying faults. We introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. Th...

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Bibliographic Details
Published in:IEEE design & test of computers 2004-05, Vol.21 (3), p.208-215
Main Authors: Appello, D., Fudoli, A., Giarda, K., Tancorre, V., Gizdarski, E., Mathew, B.
Format: Article
Language:English
Subjects:
Automatic test pattern generation
Automatic testing
Automation
Circuit faults
Circuit testing
Classification
Correlation
Diagnosis
Failure
Failure analysis
Fault detection
Fault diagnosis
Faults
Links
Logic circuits
Logic testing
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Summary:Yield improvement requires understanding failures and identifying potential sources of yield loss. We focus on diagnosing random logic circuits and classifying faults. We introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers and correlation between the ATPG patterns and the tester failure reports.
ISSN:0740-7475
2168-2356
1558-1918
2168-2364
DOI:10.1109/MDT.2004.21