Optimized NH/sub 3/ annealing Process for high-quality HfSiON gate oxide

Optimization of fabrication process in obtaining high-quality HfSiON gate-oxide metal-oxide semiconductor field-effect transistors (MOSFETs) by NH/sub 3/ post-deposition anneal (PDA) has been performed. At 600/spl deg/C anneal temperature, a longer anneal duration resulted in reduced leakage current...

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Bibliographic Details
Published in:IEEE electron device letters 2004-07, Vol.25 (7), p.465-467
Main Authors: Akbar, M.S., Cho, H.-J., Choi, R., Kang, C.S., Kang, C.Y., Choi, C.H., Rhee, S.J., Kim, Y.H., Lee, J.C.
Format: Article
Language:English
Subjects:
Annealing
Capacitance-voltage characteristics
Fabrication
FETs
Hysteresis
Leakage current
MOS devices
MOSFETs
Temperature
Voltage control
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Summary:Optimization of fabrication process in obtaining high-quality HfSiON gate-oxide metal-oxide semiconductor field-effect transistors (MOSFETs) by NH/sub 3/ post-deposition anneal (PDA) has been performed. At 600/spl deg/C anneal temperature, a longer anneal duration resulted in reduced leakage current density (J), reduced trapped charges, and lower hysteresis in capacitance-voltage curves, but with a slight increase in effective oxide thickness (EOT). Subsequent interfacial layer growth with longer anneal duration was attributed to the increase in EOT. MOSFET, fabricated by the optimized process of 600/spl deg/C, 40 s NH/sub 3/ PDA, showed superior I/sub d/--V/sub d/ (drain current-drain voltage) and charge-trapping characteristics as compared to control Hf-Silicate.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2004.830270