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Integration challenges of new materials and device architectures for IC applications

In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.

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Bibliographic Details
Main Authors: Bich-Yen Nguyen, Thean, A., White, T., Vandooren, A., Sadaka, M., Mathew, L., Barr, A., Thomas, S., Zalava, M., Da Zhang, Eades, D., Zhong-Hai Shi, Schaeffer, J., Triyoso, D., Samavedam, S., Vartanian, V., Stephen, T., Goolsby, B., Zollner, S., Liu, R., Noble, R., Thien Nguyen, Dhandapani, V., Xie, B., Xang-Dong Wang, Jiang, J., Rai, R., Sadd, M., Ramon, M., Kalpat, S., Prabhu, L., Kaushik, V., Du, Y., Dao, T., Mendicino, M., Orlowski, M., Tobin, P., Mogab, J., Venkatesan, S.
Format: Conference Proceeding
Language:English
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Summary:In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
DOI:10.1109/ICICDT.2004.1309953