A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes

We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has a restricted complexity in the number of communications to or from and the processor cannot exceed 4 for BCH codes. The resulting algorithm works in lock step ma...

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Bibliographic Details
Main Authors: Reeve, J.S., Amarasinghe, K.
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Block codes
Coding, codes
Computer science
Convolution
Decoding
Demodulation
Exact sciences and technology
Field programmable gate arrays
Hamming distance
Information, signal and communications theory
Parallel algorithms
Shift registers
Signal and communications theory
Telecommunications and information theory
Viterbi algorithm
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Summary:We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has a restricted complexity in the number of communications to or from and the processor cannot exceed 4 for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and demonstrate the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes.
DOI:10.1109/ICC.2004.1313001