Fast parallel-prefix modulo 2/sup n/+1 adders

Modulo 2/sup n/+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2/sup n/+1 adders, based on parallel-prefix carry computation units, the first architecture utilizes a fast...

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Bibliographic Details
Published in:IEEE transactions on computers 2004-09, Vol.53 (9), p.1211-1216
Main Authors: Efstathiou, C., Vergos, H.T., Nikolos, D.
Format: Article
Language:English
Subjects:
Adders
Index Terms- Binary adders
modulo 2^n+1 arithmetic
Parallel architectures
parallel-prefix adders
Residue arithmetic
RNS
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Summary:Modulo 2/sup n/+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2/sup n/+1 adders, based on parallel-prefix carry computation units, the first architecture utilizes a fast carry increment stage, whereas the second is a totally parallel-prefix solution. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and execution latency.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2004.60