TDC-based frequency synthesizer for wireless applications

We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase/...

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Bibliographic Details
Main Authors: Staszewski, R.B., Leipold, D., Chih-Ming Hung, Balsara, P.T.
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Bluetooth
Circuit properties
Circuits of signal characteristics conditioning (including delay circuits)
Design. Technologies. Operation analysis. Testing
Digital circuits
Digital control
Digital filters
Digital-to-frequency converters
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Frequency conversion
Frequency synthesizers
Integrated circuits
Oscillators
Oscillators, resonators, synthetizers
Performance analysis
Phase locked loops
Phase noise
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Description
Summary:We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase/frequency detector. When implemented in a deep-submicron CMOS, the presented architecture appears more advantageous over conventional charge-pump-based PLL, since it contains only two intrinsic phase noise sources and it does not rely on the fine voltage resolution of analog circuits. The measured close-in phase noise of -86.2 dBc/Hz and the rms phase error of 0.9/spl deg/ are adequate also for GSM applications.
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2004.1320575