A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor

A next-generation 1.6GHz 4-issue CPU supports high-end servers and has a 4MB L2 cache. The chip uses 315M transistors in a 90nm 8M CMOS process with an area of 234mm/sup 2/.

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Bibliographic Details
Main Authors: Wendell, D., Lin, J., Kaushik, P., Seshadri, S., Wang, A., Sundararaman, V., Wang, P., McIntyre, H., Kim, S., Hsu, W., Park, H., Levinsky, G., Lu, J., Chirania, M., Heald, R., Lazar, P.
Format: Conference Proceeding
Language:English
Subjects:
Applied sciences
Central Processing Unit
Circuits
Clocks
Decoding
Delay
Design. Technologies. Operation analysis. Testing
Electronics
Error correction codes
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Microprocessors
Registers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Throughput
Wire
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Description
Summary:A next-generation 1.6GHz 4-issue CPU supports high-end servers and has a 4MB L2 cache. The chip uses 315M transistors in a 90nm 8M CMOS process with an area of 234mm/sup 2/.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2004.1332596