A 10 Gb/s SONET-compliant CMOS transceiver with low cross-talk and intrinsic jitter

A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover d...

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Bibliographic Details
Main Authors: Werker, H., Mechnig, S., Holuigue, C., Ebner, C., Mitteregger, G., Romani, E., Roger, F., Blon, T., Moyal, M., Vena, M., Melodia, A., Fisher, J., de Mercey, G., Geib, H.
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
CMOS technology
Impedance
Inductors
Jitter
Phase locked loops
Phase noise
SONET
Transceivers
Voltage-controlled oscillators
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Summary:A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2004.1332649