CESAME: a test chip for the validation of a parasitic emission prediction flow in 0.18 /spl mu/m CMOS technology

Due to increasing speed and complexity, integrated circuits (ICs) are faced with severe parasitic emission problems. The internal current switching, of the order of several amperes per nanosecond, provokes important voltage drops and ringing effects on the supply lines of the IC. This noise provokes...

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Bibliographic Details
Main Authors: Vrigno, B., Bendhia, S., Courau, L., Sicard, E.
Format: Conference Proceeding
Language:English
Subjects:
Circuit testing
CMOS analog integrated circuits
CMOS integrated circuits
CMOS technology
Current measurement
Electromagnetic interference
Electromagnetic measurements
Integrated circuit measurements
Integrated circuit noise
Noise measurement
Online Access:Request full text
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Summary:Due to increasing speed and complexity, integrated circuits (ICs) are faced with severe parasitic emission problems. The internal current switching, of the order of several amperes per nanosecond, provokes important voltage drops and ringing effects on the supply lines of the IC. This noise provokes conducted emission on the external supply lines as well as radiated emission over the surface of the circuit. In order to establish in the IC design flow an evaluation of the parasitic emission, an experimental circuit has been designed in CMOS 0.18 /spl mu/m. The simulated and measured core noise are compared.
DOI:10.1109/ISEMC.2004.1349818