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A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high frequency of 480-MHz, we achieved a 10% output droop...

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Bibliographic Details
Main Authors: Schrom, G., Hazucha, P., Hahn, J., Gardner, D.S., Bloechel, B.A., Dermer, G., Narendra, S.G., Karnik, T., De, V.
Format: Conference Proceeding
Language:English
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Summary:We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high frequency of 480-MHz, we achieved a 10% output droop with only 2.5 nF of on-chip decoupling, for 0.5 A of load current. No off-chip decoupling was connected to the output. At 480 MHz the measured efficiency was 72%. At 250 MHz, the efficiency improved to 76% at the cost of a 17% droop or larger decoupling of 11.5 nF. A converter with 100 A rating would require a capacitor of 0.5 /spl mu/F, which is comparable to the size of an on-chip capacitor of a typical microprocessor.
ISSN:0275-9306
2377-6617
DOI:10.1109/PESC.2004.1354830