SOI flash memory scaling limit and design consideration based on 2-D analytical modeling

• Published in: IEEE transactions on electron devices 2004-12, Vol.51 (12), p.2054-2060
• Main Authors: Chan, A.C.K., Tsz-Yin Man, Jin He, Kam-Hung Yuen, Wai-Kit Lee, Chan, M.
• Format: Article
• Language: English
• Subjects: Applied sciences; Compact modeling; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Flash; Integrated circuit design; Integrated circuit modeling; Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon on insulator technology; silicon-on-insulator (SOI); Storage and reproduction of information; Transistors; ultrathin body (UTB)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2004.838327

In this paper, the short-channel effect in ultrathin body (UTB) SOI Flash memory cell induced by the floating-gate is investigated by a newly developed two-dimensional analytical model. A concept of effective natural length (/spl lambda//sub eff/) is introduced as a measure of the impact of the floating-gate on the scaling limit. Even though scaling the channel thickness can significantly reduce SCE in UTB MOSFET, it becomes less effective in floating-gate device due to the floating polysilicon induced gate coupling. To minimize the floating-gate induced SCEs, the drain to floating-gate coupling has to be minimized.