SEE in a 0.15 /spl mu/m fully depleted CMOS/SOI commercial Process

We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 /spl mu/m Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SE...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2004-12, Vol.51 (6), p.3621-3625
Main Authors: Makihara, A., Yamaguchi, T., Tsuchiya, Y., Arimitsu, T., Asai, H., Iide, Y., Shindou, H., Kuboyama, S., Matsuda, S.
Format: Article
Language:English
Subjects:
Circuits
CMOS process
CMOS technology
Commercial process
Degradation
Design methodology
flip-flop
Flip-flops
fully depleted CMOS/SOI
hardness-by design (HBD)
Isolation technology
latch
Latches
Signal generators
single-event effects (SEEs)
Space technology
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 /spl mu/m Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2004.839155