Stretching the limits of clock-gating efficiency in server-class processors

Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors. In this paper we first examine the realisti...

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Bibliographic Details
Main Authors: Jacobson, H., Bose, P., Zhigang Hu, Buyuktosunoglu, A., Zyuban, V., Eickemeyer, R., Eisen, L., Griswell, J., Logan, D., Balaram Sinharoy, Tendler, J.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS technology
Energy management
Jacobian matrices
Microprocessors
Pipelines
Power generation
Power system management
Technology management
Temperature
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Summary:Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors. In this paper we first examine the realistic benefits and limits of clock-gating in current generation high-performance processors (e.g. of the POWER4/spl trade/ or POWER5/spl trade/ class). We then look beyond classical clock-gating: we examine additional opportunities to avoid unnecessary clocking in real workload executions. In particular, we examine the power reduction benefits of a couple of newly invented schemes called transparent pipeline clock-gating and elastic pipeline clock-gating. Based on our experiences with current designs, we try to bound the practical limits of clock gating efficiency in future microprocessors.
ISSN:1530-0897
2378-203X
DOI:10.1109/HPCA.2005.33