An SOC test integration platform and its industrial realization

• Main Authors: CHENG, Kuo-Liang, HUANG, Jing-Reng, WANG, Chih-Wea, LO, Chih-Yen, DENQ, Li-Ming, HUANG, Chih-Tsun, WU, Cheng-Wen, HUNG, Shin-Wei, LEE, Jye-Yuan
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Area measurement; Costs; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Occupational stress; Semiconductor device measurement; Semiconductor device testing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; System testing; System-on-a-chip; Technological innovation; Testing, measurement, noise and reliability; Time measurement; Timing
• DOI: 10.1109/TEST.2004.1387394

One of the major costs in system-on-chip (SOC) development is test cost, especially the cost related to test integration. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. In this paper, we stress the practical SOC test integration issues, including real problems found in test scheduling, test IO reduction, timing of functional test, scan IO sharing, etc. A test scheduling method is proposed based on our test architecture and test access mechanism (TAM), considering IO resource constraints. Detailed scheduling further reduces the overall test time of the system chip. We also present a test wrapper architecture that supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. The chip has been designed and fabricated. The measurement results justify the approach-simple and efficient, i.e., short test integration cost, short test time, and small area overhead.