Extracting of substrate network resistances in RF CMOS transistors

Substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor is laid out...

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Bibliographic Details
Main Authors: Tabrizi, M.M., Fathi, E., Fathipour, M., Masoumi, N.
Format: Conference Proceeding
Language:English
Subjects:
Application software
Capacitance
Circuit simulation
CMOS technology
Diodes
Intelligent networks
MOSFET circuits
Radio frequency
Resistors
Semiconductor device modeling
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Summary:Substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor is laid out and all substrate resistances are extracted from I-V characteristics. Device and process simulation results for 0.25 /spl mu/m CMOS technology show that the horse-shoe structure decreases the parasitic substrate resistance by 27%. Additionally, we show that the results obtained by the traditional approximation method deviated about 31% from the exact results. Furthermore, with the proposed method, the substrate resistance values can be exactly extracted.
DOI:10.1109/SMIC.2004.1398207