Extracting of substrate network resistances in RF CMOS transistors

Substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor is laid out...

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Main Authors: Tabrizi, M.M., Fathi, E., Fathipour, M., Masoumi, N.
Format: Conference Proceeding
Language:English
Subjects:
Application software
Capacitance
Circuit simulation
CMOS technology
Diodes
Intelligent networks
MOSFET circuits
Radio frequency
Resistors
Semiconductor device modeling
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creator Tabrizi, M.M.
Fathi, E.
Fathipour, M.
Masoumi, N.
description Substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor is laid out and all substrate resistances are extracted from I-V characteristics. Device and process simulation results for 0.25 /spl mu/m CMOS technology show that the horse-shoe structure decreases the parasitic substrate resistance by 27%. Additionally, we show that the results obtained by the traditional approximation method deviated about 31% from the exact results. Furthermore, with the proposed method, the substrate resistance values can be exactly extracted.
doi_str_mv 10.1109/SMIC.2004.1398207
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1398207</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1398207</ieee_id><sourcerecordid>1398207</sourcerecordid><originalsourceid>FETCH-ieee_primary_13982073</originalsourceid><addsrcrecordid>eNp9jk0KwjAUhAMiKNoDiJt3AWvSVJtsLS26KIJ1X2JJJf6kkhdRb2-Frh0GhuGbxRAyYzRkjMplWezSMKI0DhmXIqLJgAQyEbQzFwnl8YgEiBfaicv1SrAx2WRv71TtjT1D2wA-T9h1r8Fq_2rdFZxGg17ZWiMYC4cc0mJfQjeyP9A6nJJho26ogz4nZJ5nx3S7MFrr6uHMXblP1T_i_-kX1bw6Xg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Extracting of substrate network resistances in RF CMOS transistors</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Tabrizi, M.M. ; Fathi, E. ; Fathipour, M. ; Masoumi, N.</creator><creatorcontrib>Tabrizi, M.M. ; Fathi, E. ; Fathipour, M. ; Masoumi, N.</creatorcontrib><description>Substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor is laid out and all substrate resistances are extracted from I-V characteristics. Device and process simulation results for 0.25 /spl mu/m CMOS technology show that the horse-shoe structure decreases the parasitic substrate resistance by 27%. Additionally, we show that the results obtained by the traditional approximation method deviated about 31% from the exact results. Furthermore, with the proposed method, the substrate resistance values can be exactly extracted.</description><identifier>ISBN: 9780780387034</identifier><identifier>ISBN: 0780387031</identifier><identifier>DOI: 10.1109/SMIC.2004.1398207</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application software ; Capacitance ; Circuit simulation ; CMOS technology ; Diodes ; Intelligent networks ; MOSFET circuits ; Radio frequency ; Resistors ; Semiconductor device modeling</subject><ispartof>Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004, 2004, p.219-222</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1398207$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1398207$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tabrizi, M.M.</creatorcontrib><creatorcontrib>Fathi, E.</creatorcontrib><creatorcontrib>Fathipour, M.</creatorcontrib><creatorcontrib>Masoumi, N.</creatorcontrib><title>Extracting of substrate network resistances in RF CMOS transistors</title><title>Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004</title><addtitle>SMIC</addtitle><description>Substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor is laid out and all substrate resistances are extracted from I-V characteristics. Device and process simulation results for 0.25 /spl mu/m CMOS technology show that the horse-shoe structure decreases the parasitic substrate resistance by 27%. Additionally, we show that the results obtained by the traditional approximation method deviated about 31% from the exact results. Furthermore, with the proposed method, the substrate resistance values can be exactly extracted.</description><subject>Application software</subject><subject>Capacitance</subject><subject>Circuit simulation</subject><subject>CMOS technology</subject><subject>Diodes</subject><subject>Intelligent networks</subject><subject>MOSFET circuits</subject><subject>Radio frequency</subject><subject>Resistors</subject><subject>Semiconductor device modeling</subject><isbn>9780780387034</isbn><isbn>0780387031</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNp9jk0KwjAUhAMiKNoDiJt3AWvSVJtsLS26KIJ1X2JJJf6kkhdRb2-Frh0GhuGbxRAyYzRkjMplWezSMKI0DhmXIqLJgAQyEbQzFwnl8YgEiBfaicv1SrAx2WRv71TtjT1D2wA-T9h1r8Fq_2rdFZxGg17ZWiMYC4cc0mJfQjeyP9A6nJJho26ogz4nZJ5nx3S7MFrr6uHMXblP1T_i_-kX1bw6Xg</recordid><startdate>2004</startdate><enddate>2004</enddate><creator>Tabrizi, M.M.</creator><creator>Fathi, E.</creator><creator>Fathipour, M.</creator><creator>Masoumi, N.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2004</creationdate><title>Extracting of substrate network resistances in RF CMOS transistors</title><author>Tabrizi, M.M. ; Fathi, E. ; Fathipour, M. ; Masoumi, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_13982073</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Application software</topic><topic>Capacitance</topic><topic>Circuit simulation</topic><topic>CMOS technology</topic><topic>Diodes</topic><topic>Intelligent networks</topic><topic>MOSFET circuits</topic><topic>Radio frequency</topic><topic>Resistors</topic><topic>Semiconductor device modeling</topic><toplevel>online_resources</toplevel><creatorcontrib>Tabrizi, M.M.</creatorcontrib><creatorcontrib>Fathi, E.</creatorcontrib><creatorcontrib>Fathipour, M.</creatorcontrib><creatorcontrib>Masoumi, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tabrizi, M.M.</au><au>Fathi, E.</au><au>Fathipour, M.</au><au>Masoumi, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Extracting of substrate network resistances in RF CMOS transistors</atitle><btitle>Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004</btitle><stitle>SMIC</stitle><date>2004</date><risdate>2004</risdate><spage>219</spage><epage>222</epage><pages>219-222</pages><isbn>9780780387034</isbn><isbn>0780387031</isbn><abstract>Substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor is laid out and all substrate resistances are extracted from I-V characteristics. Device and process simulation results for 0.25 /spl mu/m CMOS technology show that the horse-shoe structure decreases the parasitic substrate resistance by 27%. Additionally, we show that the results obtained by the traditional approximation method deviated about 31% from the exact results. Furthermore, with the proposed method, the substrate resistance values can be exactly extracted.</abstract><pub>IEEE</pub><doi>10.1109/SMIC.2004.1398207</doi></addata></record>
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Application software
Capacitance
Circuit simulation
CMOS technology
Diodes
Intelligent networks
MOSFET circuits
Radio frequency
Resistors
Semiconductor device modeling
title Extracting of substrate network resistances in RF CMOS transistors
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T08%3A37%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Extracting%20of%20substrate%20network%20resistances%20in%20RF%20CMOS%20transistors&rft.btitle=Digest%20of%20Papers.%202004%20Topical%20Meeting%20onSilicon%20Monolithic%20Integrated%20Circuits%20in%20RF%20Systems,%202004&rft.au=Tabrizi,%20M.M.&rft.date=2004&rft.spage=219&rft.epage=222&rft.pages=219-222&rft.isbn=9780780387034&rft.isbn_list=0780387031&rft_id=info:doi/10.1109/SMIC.2004.1398207&rft_dat=%3Cieee_6IE%3E1398207%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-ieee_primary_13982073%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1398207&rfr_iscdi=true