Combining system level modeling with assertion based verification

Assertion based verification (ABV) using the PSL language is currently gaining acceptance as an essential method for functional verification of hardware. A basic technique to implement ABV is to embed temporal assertions in RTL code. The paper describes the use of a PSL-based ABV methodology in a C+...

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Bibliographic Details
Main Authors: Dahan, A., Geist, D., Gluhovsky, L., Pidan, D., Shapir, G., Wolfsthal, Y., Benalycherif, L., Kamidem, R., Lahbib, Y.
Format: Conference Proceeding
Language:English
Subjects:
Design engineering
Gas insulated transmission lines
Hardware design languages
Libraries
Microelectronics
Natural languages
Power engineering and energy
Registers
Sugar industry
Writing
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Summary:Assertion based verification (ABV) using the PSL language is currently gaining acceptance as an essential method for functional verification of hardware. A basic technique to implement ABV is to embed temporal assertions in RTL code. The paper describes the use of a PSL-based ABV methodology in a C++-based system level modeling and simulation environment. We describe the considerations of porting a tool, which translates PSL to VHDL/Verilog, to support C++, a language which was designed for software and does not have concurrent language constructs. The translation scheme is shown to be adaptable to all C-based environments. We exemplify the wide applicability of this scheme by detailing its successful deployment in a SystemC-based industrial system-on-chip (SoC) project.
ISSN:1948-3287
1948-3295
DOI:10.1109/ISQED.2005.32