RF substrate noise characterization for CMOS 0.18 /spl mu/m

In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the deep nwell (or triple well isolation) and the P+ guard ring. The test structures were...

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Main Authors: Ishak, L.S., Keating, R.A., Chakrabarty, C.K.
Format: Conference Proceeding
Language:English
Subjects:
Circuit noise
Circuit testing
CMOS process
CMOS technology
Conductivity
Diodes
Isolation technology
Radio frequency
Silicon
Working environment noise
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Keating, R.A.
Chakrabarty, C.K.
description In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the deep nwell (or triple well isolation) and the P+ guard ring. The test structures were designed and fabricated using Silterra CMOS 0.18 /spl mu/m mixed signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (S/sub out/) in which the substrate coupling effects with and without deep nwell were characterized.
doi_str_mv 10.1109/RFM.2004.1411075
format conference_proceeding
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Circuit noise
Circuit testing
CMOS process
CMOS technology
Conductivity
Diodes
Isolation technology
Radio frequency
Silicon
Working environment noise
title RF substrate noise characterization for CMOS 0.18 /spl mu/m
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