Accurate RT-level power estimation using up-down encoding

RT-level power estimation is to quickly predict the total switching activity in a logic design without resorting to the time-consuming gate-level simulation. We propose an up-down encoding scheme in conjunction with linear approximation to improve the estimation accuracy. In order to take into accou...

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Bibliographic Details
Main Authors: Ming-Yi Sum, Shi-Yu Huang, Chia-Chien Weng, Kai-Shuang Chang
Format: Conference Proceeding
Language:English
Subjects:
Encoding
Energy consumption
Equations
Estimation error
Extrapolation
Linear approximation
Logic design
Predictive models
Statistics
Switching circuits
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Summary:RT-level power estimation is to quickly predict the total switching activity in a logic design without resorting to the time-consuming gate-level simulation. We propose an up-down encoding scheme in conjunction with linear approximation to improve the estimation accuracy. In order to take into account the temporal correlation in the input patterns, we use a cycle-by-cycle modeling scheme. On top of it, each primary input is further encoded into two binary variables to faithfully reflect its switching behavior. The proposed method has been realized as a tool that can fit into the commercial design flow and tested by a number of datapath design blocks. Experimental results show that the estimation error is only 1.3 %.
DOI:10.1109/APCCAS.2004.1412693