An associative processing module for a heterogeneous vision architecture

The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes i...

Full description

Saved in:
Bibliographic Details
Published in:IEEE MICRO 1992-06, Vol.12 (3), p.42-55
Main Authors: Storer, R., Pout, M.R., Thomson, A.R., Dagless, E.L., Duller, A.W.G., Marriott, A.P., Hicks, P.J.
Format: Article
Language:English
Subjects:
Associative processing
Computer architecture
Computer vision
Concurrent computing
Digital signal processing chips
Feature extraction
Parallel processing
Pipelines
Signal processing
Very large scale integration
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes images and extract features, and a MIMD network of transputers processes extracted objects in parallel. The array's VLSI implementation, the processing modes available due to the use of content-addressable memory, and the means of achieving efficient 2-D interprocessor communication in the linear array are described. An application as a vehicle number plate recognition system is presented.< >
ISSN:0272-1732
1937-4143
DOI:10.1109/40.141602