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An associative processing module for a heterogeneous vision architecture
The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes i...
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| Published in: | IEEE MICRO 1992-06, Vol.12 (3), p.42-55 |
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| Main Authors: | , , , , , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c275t-926209ea2d1c07415211921ce09cdb516b924fe98875590cb2c6fca0963ebf443 |
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| cites | cdi_FETCH-LOGICAL-c275t-926209ea2d1c07415211921ce09cdb516b924fe98875590cb2c6fca0963ebf443 |
| container_end_page | 55 |
| container_issue | 3 |
| container_start_page | 42 |
| container_title | IEEE MICRO |
| container_volume | 12 |
| creator | Storer, R. Pout, M.R. Thomson, A.R. Dagless, E.L. Duller, A.W.G. Marriott, A.P. Hicks, P.J. |
| description | The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes images and extract features, and a MIMD network of transputers processes extracted objects in parallel. The array's VLSI implementation, the processing modes available due to the use of content-addressable memory, and the means of achieving efficient 2-D interprocessor communication in the linear array are described. An application as a vehicle number plate recognition system is presented.< > |
| doi_str_mv | 10.1109/40.141602 |
| format | article |
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| fulltext | fulltext |
| identifier | ISSN: 0272-1732 |
| ispartof | IEEE MICRO, 1992-06, Vol.12 (3), p.42-55 |
| issn | 0272-1732 1937-4143 |
| language | eng |
| recordid | cdi_ieee_primary_141602 |
| source | IEEE Xplore (Online service) |
| subjects | Associative processing Computer architecture Computer vision Concurrent computing Digital signal processing chips Feature extraction Parallel processing Pipelines Signal processing Very large scale integration |
| title | An associative processing module for a heterogeneous vision architecture |
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