A new cell-based performance metric for novel CMOS device architectures

This paper introduces, for the first time, a method for assessing the impact of CMOS technology choices on dynamic system level performance. The method is applied to the evaluation of five different device architectures, which include bulk, FDSOI, and multi-gate devices. Timing and power information...

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Bibliographic Details
Main Authors: Christie, P., Heringa, A., Doornbos, G., Kumar, A., Nguyen, V.H., Ng, R.K.M., Garg, M.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Applied sciences
Capacitance
CMOS technology
Delay
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Measurement
Medical simulation
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Timing
Voltage
Wires
Online Access:Request full text
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Summary:This paper introduces, for the first time, a method for assessing the impact of CMOS technology choices on dynamic system level performance. The method is applied to the evaluation of five different device architectures, which include bulk, FDSOI, and multi-gate devices. Timing and power information at the standard cell level is extracted for each of the devices and used to simulate their performance embedded within a cell array of 230,400 cells.
DOI:10.1109/IEDM.2004.1419279