A low-power CMOS-VLSI circuit for signal conditioning in integrated capacitive sensors

• Main Authors: Dimitropoulos, P.D., Nikolaidis, S.P., Karampatzakis, D.P., Stamoulis, G.I.
• Format: Conference Proceeding
• Language: English
• Subjects: Capacitive sensors; Clocks; CMOS process; CMOS technology; Communication, education, history, and philosophy; Exact sciences and technology; Fundamental areas of phenomenology (including applications); General equipment and techniques; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuit interconnections; Integrated circuit technology; Laser optical systems: design and operation; Manufacturing processes; Monolithic integrated circuits; Operational amplifiers; Optics; Parasitic capacitance; Physics; Physics literature and publications; Resonators, cavities, amplifiers, arrays, and rings; Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing
• DOI: 10.1109/ICSENS.2004.1426136

Capacitive sensor manufacturing processes are rarely compatible with CMOS technologies and, thus, monolithic integration of sensing device and signal-conditioning IC is often not possible. Multi-chip packaging and wire bonding is employed instead, to interconnect sensor and IC dies. In such cases, sensor capacitance is comparable or even smaller than the parasitic interconnection capacitance, while interconnection parasitic resistance inserts additional signal distortion. The signal-conditioning IC must be designed to compensate for these parasitic effects. Switched-capacitor ICs may fulfil such specifications but the use of several operational amplifiers and intricate clocking schemes increase design complexity, die-size, and power consumption, which is inappropriate for wireless applications. In this work a low-power switched-capacitor IC for sub-fF capacitance measurements is presented. The proposed design requires two non-overlapping clocks but no operational amplifiers. It shows excellent robustness against interconnection parasitics, transistor dimensional mismatches, temperature, and process variations.