An analog floating-gate node for Supervised learning

We present an improved analog floating-gate pFET synapse that implements a supervised learning algorithm similar to the least mean square (LMS) learning rule. Weight decay plays a key role in several learning rules; this floating-gate synapse exhibits this behavior. We examine implications of the we...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2005-05, Vol.52 (5), p.834-845
Main Authors: Hasler, P., Dugger, J.
Format: Article
Language:English
Subjects:
Adaptation model
Adaptive node
Algorithms
analog systems
Circuits
Computational modeling
Correlation
Decay
floating-gate circuits
Learning
Learning systems
least mean square (LMS)
Least mean squares
Least squares approximation
Mathematical model
Minimization
Network-on-a-chip
Networks
Steady-state
Supervised learning
Synapses
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We present an improved analog floating-gate pFET synapse that implements a supervised learning algorithm similar to the least mean square (LMS) learning rule. Weight decay plays a key role in several learning rules; this floating-gate synapse exhibits this behavior. We examine implications of the weight decay appearing in the correlation learning rule realized in the floating-gate synapse and provide experimental data characterizing the synapse and its performance in one-input and two-input LMS networks. Analog floating-gate synapses will enable larger-scale, on-chip learning networks than previously possible.
ISSN:1549-8328
1057-7122
1558-0806
DOI:10.1109/TCSI.2005.846663