Design and implementation of FPGA router for efficient utilization of heterogeneous routing resources

The routing resources available in recent FPGA architectures (e.g., Xilinx Virtex-II) are very different from the older generation of FPGAs (e.g., Xilinx XC4000). The latest FPGA architectures have heterogeneous routing resources which include directly driven wires of different lengths and connectiv...

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Bibliographic Details
Main Authors: Deepak Rautela, Rajendra Katti
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Cost function
Field programmable gate arrays
Iterative algorithms
Routing
Stress
Switches
Very large scale integration
Wires
Wiring
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Summary:The routing resources available in recent FPGA architectures (e.g., Xilinx Virtex-II) are very different from the older generation of FPGAs (e.g., Xilinx XC4000). The latest FPGA architectures have heterogeneous routing resources which include directly driven wires of different lengths and connectivity. Since routing resources in FPGAs are fixed, it is very important for the routing algorithms to fully exploit the potential of new routing architectures. FPGA routing architectures are usually represented as a routing resource graph (RRG). In this paper we present a simplified scheme to build the RRG for FPGA architectures with heterogeneous routing resources. Using our RRG construction scheme we have built a mutability driven FPGA router named "Bison". We also present two dynamic weight update based heuristics which we have incorporated into the router, so that efficient utilization of routing resources can be achieved.
ISSN:2159-3469
2159-3477
DOI:10.1109/ISVLSI.2005.26