A coarse-grain phased logic CPU

This paper describes an asynchronous design tool flow known as phased logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping o...

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Bibliographic Details
Published in:IEEE transactions on computers 2005-07, Vol.54 (7), p.788-799
Main Authors: Reese, R.B., Thornton, M.A., Traver, C.
Format: Article
Language:English
Subjects:
asynchronous
Asynchronous logic circuits
Bundling
Delay
Delay effects
Floating point arithmetic
Index Terms- Automatic synthesis
Latches
Libraries
Logic
Logic design
Microcontrollers
micropipelines
Pipeline processing
pipelined processor
self-timed
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Summary:This paper describes an asynchronous design tool flow known as phased logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18/spl mu/ and 0.13/spl mu/) and a five-stage pipelined MIPs-compatible integer unit mapped to the 0.13/spl mu/ library. The design style includes a feature known as early evaluation, which is a generalized form of bypass that allows the self-timed design to recover some of the inherent latch delay penalty in micropipelines.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2005.105