Impact of mask alignment on the tunneling field effect transistor (TFET)

The tunneling field effect transistor (TFET) is a standard CMOS process flow compatible device which shows improved short channel characteristics and lower static power consumption. The device is generated by the p-implant layer overlapping the source extension. A test-structure is proposed to inves...

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Bibliographic Details
Main Authors: Nirschl, T., Schaper, U., Einfeld, J., Henzler, S., Sterkel, M., Singer, J., Fulde, M., Hansch, W., Georgakos, G., Schmitt-Landsiedell, D.
Format: Conference Proceeding
Language:English
Subjects:
Charge carrier density
CMOS process
CMOS technology
Diodes
Electrons
Energy consumption
FETs
MOSFET circuits
Testing
Tunneling
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Description
Summary:The tunneling field effect transistor (TFET) is a standard CMOS process flow compatible device which shows improved short channel characteristics and lower static power consumption. The device is generated by the p-implant layer overlapping the source extension. A test-structure is proposed to investigate the impact of the alignment of the p-implant mask on the device characteristics.
ISSN:1071-9032
2158-1029
DOI:10.1109/ICMTS.2005.1452216