An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

This paper describes a digital pulsewidth modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resol...

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Main Authors: Foley, R.F., Kavanagh, R.C., Marnane, W.P., Egan, M.G.
Format: Conference Proceeding
Language:English
Subjects:
Counting circuits
Delay
Digital modulation
Field programmable gate arrays
Frequency
Power generation
Pulse modulation
Pulse width modulation
Pulsed power supplies
Space vector pulse width modulation
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creator Foley, R.F.
Kavanagh, R.C.
Marnane, W.P.
Egan, M.G.
description This paper describes a digital pulsewidth modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.
doi_str_mv 10.1109/APEC.2005.1453214
format conference_proceeding
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identifier ISSN: 1048-2334
ispartof Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, 2005. APEC 2005, 2005, Vol.3, p.1412-1418 Vol. 3
issn 1048-2334
2470-6647
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source IEEE Xplore All Conference Series
subjects Counting circuits
Delay
Digital modulation
Field programmable gate arrays
Frequency
Power generation
Pulse modulation
Pulse width modulation
Pulsed power supplies
Space vector pulse width modulation
title An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation
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