A 32/spl times/24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure

We introduce the advanced rectangular styled Wallace-tree construction method. This method realizes a compact layout and high-speed operation of multiplier. A 32/spl times/24-bit multiplier-accumulator was constructed using this new method. 540 um/spl times/840 um area size and 300 MHz clock speed w...

Full description

Saved in:
Bibliographic Details
Main Authors: Itoh, N., Tsukamoto, Y., Shibagaki, T., Nii, K., Takata, H., Makino, H.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Clocks
CMOS logic circuits
CMOS process
CMOS technology
Degradation
Flash memory
Large scale integration
Microcontrollers
Ubiquitous computing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We introduce the advanced rectangular styled Wallace-tree construction method. This method realizes a compact layout and high-speed operation of multiplier. A 32/spl times/24-bit multiplier-accumulator was constructed using this new method. 540 um/spl times/840 um area size and 300 MHz clock speed were achieved using 0.15 um CMOS logic process technology with flash memory.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2005.1464527