A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter

• Main Authors: Akino, T., Matsuura, K., Yasunaga, A.
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Capacitance; Circuit simulation; CMOS logic circuits; Inverters; MOSFETs; Semiconductor device modeling; Substrates; Systems engineering and theory; Threshold voltage
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2005.1464622

A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the gated lateral npn or pnp BJT inherent of nor p-channel MOSFETs. Forward current is applied to the base terminal of the channel MOSFETs, with a normal pull-up or pull-down MOSFET as a current source, where each drain terminal is connected to the corresponding base terminal of the inverter. A logic scheme is also proposed to control the gates of the pull-up or pull-down MOSFETs in switching states using output signals made from two CMOS inverters with different resistance ratios. Circuit simulation using 0.35 /spl mu/m BSIM3v3 model parameters for MOSFETs and a current gain of /spl beta//sub F/=100 for BJTs, shows the speed of a domino CMOS full adder with the U-BiCMOS inverter (DCFAU) to be 1.9 times faster than that of a static CMOS full adder with 3-stage CMOS inverter (SCFA3S) designed on the basis of logical effort for driving a load capacitance of 0.3542 pF at V/sub dd/=1.2 V. The energy consumption of the DCFAU is also approximately 20% lower than that of the SCFA3S.