Implementation of a cycle by cycle variable speed processor

This paper presents an automatic variable speed processor (VSP) with the ability to change its clock rate on a cycle by cycle basis, according to program instructions being in the pipeline. To demonstrate the concept, we are using an Altera Nios processor coupled to a variable period clock synthesiz...

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Bibliographic Details
Main Authors: Epassa, H.G., Boyer, F.R., Savaria, Y.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Clocks
Dynamic voltage scaling
Energy consumption
Frequency
Microelectronics
Microprocessors
Proposals
Scheduling algorithm
Voltage control
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Description
Summary:This paper presents an automatic variable speed processor (VSP) with the ability to change its clock rate on a cycle by cycle basis, according to program instructions being in the pipeline. To demonstrate the concept, we are using an Altera Nios processor coupled to a variable period clock synthesizer (VPCS) that is used as our variable speed clock generator. The clock period variations give a speedup, with little impact on energy consumption, and that speedup can be traded for energy reduction using voltage scaling. Our proposals are supported with a prototype implemented on the Altera embedded system development board that embeds a Strafix FPGA.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2005.1465342