A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

• Main Authors: Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo
• Format: Conference Proceeding
• Language: English
• Subjects: Automatic voltage control; CMOS technology; Costs; Data compression; Decoding; Energy consumption; Hardware; MPEG 4 Standard; Very large scale integration; Video compression
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2005.1466034

The demand of high quality video and high data compression enables MPEG-4 AVC/H.264 to adopt the context-based adaptive variable length code (CAVLC) technique contrary to the traditional MPEG-4 VLC techniques. The paper presents a novel, low-cost, high-performance VLSI architecture design for MPEG-4 AVC/H.264 CAVLC decoding. We exploit five different techniques to reduce both the hardware cost and power consumption, and to increase the data throughput rate. They are PCCF (partial combinational component freezing), HLLT (hierarchical logic for look-up tables), ZTEBA (zero-left table elimination by arithmetic), IDS (interleaved double stacks), and ZCS (zero codeword skip). The proposed design can decode every syntax element per cycle. The synthesis result shows that the design achieves maximum speed at 175 MHz. When we synthesize the proposed design at the clock constraint of 125 MHz, the hardware cost is about 4720 gates under a 0.18 /spl mu/m CMOS technology, which achieves the real-time processing requirement for H.264 video decoding on HD1080i format video.