Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration

Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC architectures is a key enabler to manage this comp...

Full description

Saved in:
Bibliographic Details
Main Authors: Bouchhima, A., Bacivarovx, I., Youssef, W., Bonaciu, M., Jerraya, A.A.
Format: Conference Proceeding
Language:English
Subjects:
Computational modeling
Computer architecture
Costs
Hardware
Instruction sets
Laboratories
MPEG 4 Standard
Productivity
Strontium
Wires
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC architectures is a key enabler to manage this complexity and thus to enhance design productivity. In this paper, we describe an abstract, high level CPU subsystem model that captures the specificities of such MP-SoC architectures, along with a timed co-simulation environment to perform early exploration of the entire HW/SW design. The model is based on the Hardware Abstraction Layer (HAL) concept allowing the validation of complex applications written on top of real-life operating systems. Experimentation with a MPEG4 application proves the interest of the proposed methodology.
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2005.1466501