Successful fault isolation of bit line leakage and leakage suppression by ILD optimization in embedded flash memory

This paper discussed specifically by focusing on failure analysis study for the successful fault isolation of bit line to bit line (BL) leakage and the formation mechanism of electrical conducting path inside inter level dielectric (ILD) oxide between bit lines in flash cell arrays that has extra to...

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Bibliographic Details
Main Authors: Nam Sung Kim, Yang Bum Lee, Wong Wing Yew, Mukhopadhyay, M., Eng Keong Ho, Kuan, H.P., Shukla, D., Sang Hyun Han, Inn Swee Goh
Format: Conference Proceeding
Language:English
Subjects:
Character generation
Charge pumps
Circuit faults
Computer aided manufacturing
Failure analysis
Flash memory
Leakage current
Surfaces
Tellurium
Voltage
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Summary:This paper discussed specifically by focusing on failure analysis study for the successful fault isolation of bit line to bit line (BL) leakage and the formation mechanism of electrical conducting path inside inter level dielectric (ILD) oxide between bit lines in flash cell arrays that has extra topography resulting from two stacked poly-Si layers, which causes the abnormal leakage current during the initial cycling test (a few times of erasing and programming) for flash memory device using high voltage application. In addition, we demonstrate the suppression of this leakage current by optimizing ILD deposition process, resulting in the significant yield improvement as well as better process margin across a wafer.
ISSN:1946-1542
1946-1550
DOI:10.1109/IPFA.2005.1469127