Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/...

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Main Authors: Hou-Yu Chen, Chang-Yun Chang, Chien-Chao Huang, Tang-Xuan Chung, Sheng-Da Liu, Jiunn-Ren HwangYi-Hsuan Liu, Yu-Jun Chou, Hong-Jang Wu, King-Chang Shu, Chung-Kan Huang, Jan-Wen You, Jaw-Jung Shin, Chun-Kuang Chen, Chia-Hui Lin, Ju-Wang Hsu, Bao-Chin Perng, Pang-Yen Tsai, Chi-Chun Chen, Jyu-Horng Shieh, Han-Jan Tao, Shin-Chang Chen, Tsai-Sheng Gau, Fu-Liang Yang
Format: Conference Proceeding
Language:English
Subjects:
Analog circuits
CMOS technology
Dielectrics
Fabrication
Gate leakage
Lithography
Low-frequency noise
Silicon on insulator technology
Substrates
Thickness control
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Summary:For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.
ISSN:0743-1562
DOI:10.1109/.2005.1469194