CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

We demonstrate a novel CMP-less dual hard mask scheme for the integration of fully silicided gates in FinFETs by simultaneous silicidation of the gate, source and the drain. V/sub T/ of 0.18V and -0.2V are demonstrated for 50nm gate length NFET and PFET respectively. Competitive I/sub on/-I/sub off/...

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Main Authors: Anil, K.G., Verheyen, P., Collaert, N., Dixit, A., Kaczer, B., Snow, J., Vos, R., Locorotondo, S., Degroote, B., Shi, X., Rooyackers, R., Mannaert, G., Brus, S., Yim, Y.S., Lauwers, A., Goodwin, M., Kittl, J.A., van Dal, M., Richard, O., Veloso, A., Kubicek, S., Beckx, S., Boullart, W., De Meyer, K., Absil, P., Jurczak, M., Biesemans, S.
Format: Conference Proceeding
Language:English
Subjects:
Doping
FinFETs
Germanium silicon alloys
Implants
Instruments
Microelectronics
Silicidation
Silicon germanium
Snow
Threshold voltage
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Summary:We demonstrate a novel CMP-less dual hard mask scheme for the integration of fully silicided gates in FinFETs by simultaneous silicidation of the gate, source and the drain. V/sub T/ of 0.18V and -0.2V are demonstrated for 50nm gate length NFET and PFET respectively. Competitive I/sub on/-I/sub off/ of 960uA/um-140nA/um for NFET and 620uA/um-100nA/um for PFET were obtained at V/sub D/=l .3V for an EOT of 1.8nm.
ISSN:0743-1562
DOI:10.1109/.2005.1469266