Capacitance coefficients for VLSI multilevel metallization lines

The problem of reducing the complexity of parasitic capacitance evaluation of interconnection lines in a multilevel stratified dielectric medium (a good approximation for VLSI) is considered. We start out with a review of the Green's function method for the Si-SiO 2 composite and its derivation...

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Published in:IEEE transactions on electron devices 1987-03, Vol.34 (3), p.644-649
Main Authors: Zhen-Qiu Ning, Dewilde, P.M., Neerhoff, F.L.
Format: Article
Language:English
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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description The problem of reducing the complexity of parasitic capacitance evaluation of interconnection lines in a multilevel stratified dielectric medium (a good approximation for VLSI) is considered. We start out with a review of the Green's function method for the Si-SiO 2 composite and its derivation via the Fourier integral approach. Next, a piecewise linear finite-element technique is proposed to solve the integral equations that relate charges to potentials and lead to the desired capacitance matrix. We show by example that the proposed method is both less complex than methods based on piecewise constant surface charge distributions and equally accurate. This supports the accuracy and usefulness of the technique for IC design.
doi_str_mv 10.1109/T-ED.1987.22975
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subjects Applied sciences
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
title Capacitance coefficients for VLSI multilevel metallization lines
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