A fully-integrated low power direct conversion transmitter with fractional-N PLL using a fast AFC technique for CDMA applications

The paper presents a fully integrated low power direct conversion transmitter IC for CDMA applications. To reduce the power consumption and reduce switching time, a fractional-N frequency synthesizer with an internal VCO is integrated into the transmitter IC and an N-target algorithm is proposed to...

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Bibliographic Details
Main Authors: Myung-Woon Hwang, Jeong-Cheol Lee, Sungho Beck, Seungyup Yoo, Kyoohyun Lim, Hyosun Jung, Tschang-Hi Lee, Kyung-lok Kim, Gyu-Hyeong Cho, Sangwoo Han
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Automatic frequency control
Calibration
Energy consumption
Frequency synthesizers
Integrated circuit synthesis
Multiaccess communication
Phase locked loops
Transmitters
Voltage-controlled oscillators
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Summary:The paper presents a fully integrated low power direct conversion transmitter IC for CDMA applications. To reduce the power consumption and reduce switching time, a fractional-N frequency synthesizer with an internal VCO is integrated into the transmitter IC and an N-target algorithm is proposed to implement automatic frequency calibration (AFC). Total locking time is approximately 200 /spl mu/s, including 80 /spl mu/s AFC lock time. Total current consumption for -80 dBm, -10 dBm, and 8 dBm output power are 27 mA, 33 mA, and 60 mA, respectively. This chip is housed in a small 5 mm /spl times/ 5 mm 32 pin MLF package.
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2005.1489905