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SPICE modeling of MOSFETs in deep submicron
As the mainstream MOS technology is scaling into nanometer sizes, the development of physical and predictive models for circuit simulation that cover geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major goal. The paper addresses the scaling, trends and their limiting fa...
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Main Authors: | , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Citations: | Items that cite this one |
Online Access: | Request full text |
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Summary: | As the mainstream MOS technology is scaling into nanometer sizes, the development of physical and predictive models for circuit simulation that cover geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major goal. The paper addresses the scaling, trends and their limiting factors and follows through the evolution of the three MOSFET model generations of SPICE: from the Berkeley Levels 1, 2, 3 to the latest BSIM3v3, BSIM4, MM11, EKV, and SP2001. MOSFET models are examined, emphasizing device physics and mathematical techniques for numerical calculation. |
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DOI: | 10.1109/ISSE.2004.1490430 |